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LT6301 Dual 500mA, Differential xDSL Line Driver in 28-Lead TSSOP Package
FEATURES
s s
DESCRIPTIO
s s s s s s s s s
Drives Two Lines from One Package Exceeds All Requirements For Full Rate, Downstream ADSL Line Drivers Power Enhanced 28-Lead TSSOP Package Power Saving Adjustable Supply Current 500mA Minimum IOUT 11.1V Output Swing, VS = 12V, RL = 100 10.9V Output Swing, VS = 12V, IL = 250mA Low Distortion: - 82dBc at 1MHz, 2VP-P Into 50 200MHz Gain Bandwidth 600V/s Slew Rate Specified at 12V and 5V
The LT(R)6301 is a 500mA minimum output current, quad op amp with outstanding distortion performance. The amplifiers are gain-of-ten stable, but can be easily compensated for lower gains. The extended output swing allows for lower supply rails to reduce system power. Supply current is set with an external resistor to optimize power dissipation. The LT6301 features balanced, high impedance inputs with low input bias current and input offset voltage. Active termination is easily implemented for further system power reduction. Short-circuit protection and thermal shutdown ensure the device's ruggedness. The outputs drive a 100 load to 11.1V with 12V supplies, and 10.9V with a 250mA load. The LT6301 is a functional replacement for the LT1739 and LT1794 in xDSL line driver applications and requires no circuit changes. The LT6301 is available in the very small, thermally enhanced, 28-lead TSSOP package for maximum port density in line driver applications.
, LTC and LT are registered trademarks of Linear Technology Corporation.
APPLICATIO S
s s s s s
High Density ADSL Central Office Line Drivers High Efficiency ADSL, HDSL2, SHDSL Line Drivers Buffers Test Equipment Amplifiers Cable Drivers
TYPICAL APPLICATIO
High Efficiency 12V Supply ADSL Line Driver
12V 24.9k +IN
+
1/4 LT6301
SHDN
12.7 TWO COMPLETE ADSL LINE DRIVERS PROVIDED WITH ONE LT6301 PACKAGE
-
1k 110 1000pF
1:2*
* *
110
1k *COILCRAFT X8390-A OR EQUIVALENT ISUPPLY = 10mA PER AMPLIFIER WITH RSHDN = 24.9k
6301 TA01
-
1/4 LT6301 -IN
12.7 SHDNREF
+
-12V
U
100
sn6301 6301f
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1
LT6301
ABSOLUTE MAXIMUM RATINGS
(Note 1)
PACKAGE/ORDER INFORMATION
TOP VIEW V- -IN A +IN A SHDN1 SHDNREF1 +IN B -IN B -IN C +IN C 1 2 3 4 5 6 7 8 9 C B A 28 V-
Supply Voltage (V + to V -) ................................. 13.5V Input Current ..................................................... 10mA Output Short-Circuit Duration (Note 2) ........... Indefinite Operating Temperature Range ............... - 40C to 85C Specified Temperature Range (Note 3) .. - 40C to 85C Junction Temperature .......................................... 150C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LT6301CFE LT6301IFE
27 V - 26 OUT A 25 V + 24 V + 23 OUT B 22 V - 21 V - 20 OUT C 19 V + 18 V + 17 OUT D
SHDN2 10 SHDNREF2 11 +IN D 12 -IN D 13 V - 14 D
16 V - 15 V -
FE PACKAGE 28-LEAD PLASTIC TSSOP
TJMAX = 150C, JA = 25C/W (NOTE 4) UNDERSIDE METAL CONNECTED TO V -
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The q denotes the specifications which apply over the full specified temperature range, otherwise specifications are at TA = 25C. VCM = 0V, pulse tested, 5V VS 12V, VSHDNREF = 0V, RBIAS = 24.9k between V + and SHDN unless otherwise noted. (Note 3)
SYMBOL VOS PARAMETER Input Offset Voltage
q
CONDITIONS
MIN
TYP 1
MAX 5.0 7.5 5.0 7.5 500 800 4 6 500 800
UNITS mV mV mV mV V/C nA nA A A nA nA nV/Hz pA/Hz M M pF V V dB dB
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Input Offset Voltage Matching Input Offset Voltage Drift IOS IB Input Offset Current
(Note 6)
q q q
0.3 10 100 0.1
q
Input Bias Current Input Bias Current Matching (Note 6)
q
100 8 0.8
q
en in RIN CIN
Input Noise Voltage Density Input Noise Current Density Input Resistance Input Capacitance Input Voltage Range (Positive) Input Voltage Range (Negative)
f = 10kHz f = 10kHz VCM = (V + - 2V) to (V -+ 2V) Differential (Note 5) (Note 5) VCM = (V + - 2V) to (V - + 2V)
q
5
50 6.5 3 -1 V- + 1 83 V+
q q
V+
-2
V- + 2
CMRR
Common Mode Rejection Ratio
74 66
2
U
W
U
U
WW
W
LT6301
ELECTRICAL CHARACTERISTICS
The q denotes the specifications which apply over the full specified temperature range, otherwise specifications are at TA = 25C. VCM = 0V, pulse tested, 5V VS 12V, VSHDNREF = 0V, RBIAS = 24.9k between V + and SHDN unless otherwise noted. (Note 3)
SYMBOL PSRR AVOL PARAMETER Power Supply Rejection Ratio Large-Signal Voltage Gain CONDITIONS VS = 4V to 12V
q
MIN 74 66 63 57 60 54 10.9 10.7 10.6 10.4 3.7 3.5 3.6 3.4 500
q
TYP 88 76 70 11.1 10.9 4 3.9 1200 10 8 6 4
MAX
UNITS dB dB dB dB dB dB V V V V V V V V mA
VS = 12V, VOUT = 10V, RL = 40
q
VS = 5V, VOUT = 3V, RL = 25
q
VOUT
Output Swing
VS = 12V, RL = 100
q
VS = 12V, IL = 250mA
q
VS = 5V, RL = 25
q
VS = 5V, IL = 250mA
q
IOUT IS
Maximum Output Current Supply Current per Amplifier
VS = 12V, RL = 1 VS = 12V, RBIAS = 24.9k (Note 7) VS = 12V, RBIAS = 32.4k (Note 7) VS = 12V, RBIAS = 43.2k (Note 7) VS = 12V, RBIAS = 66.5k (Note 7) VS = 5V, RBIAS = 24.9k (Note 7)
q
8.0 6.7
13.5 15.0
mA mA mA mA mA mA mA mA mA dB dB V/s V/s dBc dBc MHz
2.2 1.8
3.4 0.1 0.3
5.0 5.8 1 1
Supply Current in Shutdown Output Leakage in Shutdown Channel Separation SR HD2 HD3 GBW Slew Rate Differential 2nd Harmonic Distortion Differential 3rd Harmonic Distortion Gain Bandwidth
VSHDN = 0.4V VSHDN = 0.4V VS = 12V, VOUT = 10V, RL = 40 (Note 8)
q
80 77 300 100
110 600 200 - 85 - 82 200
VS = 12V, AV = - 10, (Note 9) VS = 5V, AV = -10, (Note 9) VS = 12V, AV = 10, 2VP-P, RL = 50, 1MHz VS = 12V, AV = 10, 2VP-P, RL = 50, 1MHz f = 1MHz
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: Applies to short circuits to ground only. A short circuit between the output and either supply may permanently damage the part when operated on supplies greater than 10V. Note 3: The LT6301C is guaranteed to meet specified performance from 0C to 70C and is designed, characterized and expected to meet these extended temperature limits, but is not tested at - 40C and 85C. The LT6301I is guaranteed to meet the extended temperature limits. Note 4: Thermal resistance varies depending upon the amount of PC board metal attached to Pins 1, 14, 15, 28 and the exposed bottom side metal of the device. If the maximum dissipation of the package is exceeded, the device will go into thermal shutdown and be protected.
Note 5: Guaranteed by the CMRR tests. Note 6: Matching is between amplifiers A and B or between amplifiers C and D. Note 7: RBIAS is connected between V + and each SHDN pin, with each SHDNREF pin grounded. Note 8: Channel separation is measured between amplifiers A and B and between amplifiers C and D. Channel separation between any other combination of amplifiers is guaranteed by design as two separate die are used in the package. Note 9: Slew rate is measured at 5V on a 10V output signal while operating on 12V supplies and 1V on a 3V output signal while operating on 5V supplies.
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LT6301 TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Ambient Temperature
15 14 VS = 12V RBIAS = 24.9k TO SHDN VSHDNREF = 0V
ISUPPLY PER AMPLIFIER (mA)
COMMON MODE RANGE (V)
13 12 11 10 9 8 7 6
IBIAS (nA)
5 -50
-30
-10 10 30 50 TEMPERATURE (C)
Input Noise Spectral Density
100 TA = 25C VS = 12V IS PER AMPLIFIER = 10mA en 100
OUTPUT SATURATION VOLTAGE (V)
INPUT VOLTAGE NOISE (nV/Hz)
10
ISC (mA)
1
in
0.1 1 10 100 1k FREQUENCY (Hz) 10k
Open-Loop Gain and Phase vs Frequency
120 100 80 60 GAIN (dB) 40 20 0 GAIN TA = 25C VS = 12V AV = -10 RL = 100 IS PER AMPLIFIER = 10mA 1M 10M FREQUENCY (Hz) 100M
6300 G07
PHASE
-3dB BANDWIDTH (MHz)
30 25 20 15 10 5 0 2 4 6 8 10 12 14 SUPPLY CURRENT PER AMPLIFIER (mA)
6301 G08
-40 -80 -120 -160 -200 -240 -280
SLEW RATE (V/s)
-20 -40 -60
-80 100k
4
UW
70
6301 G01
6301 G04
Input Common Mode Range vs Supply Voltage
V+ -0.5 -1.0 -1.5 -2.0 TA = 25C VOS > 1mV
200
Input Bias Current vs Ambient Temperature
VS = 12V 180 IS PER AMPLIFIER = 10mA 160 140 120 100 80 60 40 20
2.0 1.5 1.0 0.5 V-
90
2
4
8 10 6 SUPPLY VOLTAGE (V)
12
14
6301 G02
0 -50
-30
10 30 50 -10 TEMPERATURE (C)
70
90
6301 G03
Output Short-Circuit Current vs Ambient Temperature
800 780 VS = 12V IS PER AMPLIFIER = 10mA V+ -0.5 -1.0 -1.5
Output Saturation Voltage vs Ambient Temperature
VS = 12V RL = 100 ILOAD = 250mA
INPUT CURRENT NOISE (pA/Hz) PHASE (DEG)
760 740 720 700 680 660 640 620 SOURCING SINKING
10
1
1.5 1.0 0.5 V- - 50 -30 -10
ILOAD = 250mA RL = 100
0.1 100k
600 -50
-30
30 -10 10 50 TEMPERATURE (C)
70
90
50 30 10 TEMPERATURE (C)
70
90
6301 G06
6301 G05
-3dB Bandwidth vs Supply Current
120 80 40 0
Slew Rate vs Supply Current
1000 900 800 700 600 500 400 300 200 100 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SUPPLY CURRENT PER AMPLIFIER (mA)
6301 G09
45 40 35
TA = 25C VS = 12V AV = 10 RL = 100
TA = 25C VS = 12V AV = -10 RL = 1k
RISING FALLING
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LT6301 TYPICAL PERFOR A CE CHARACTERISTICS
CMRR vs Frequency
100
COMMON MODE REJECTION RATIO (dB)
90 80 70 60 50 40 30 20 10 0 0.1
POWER SUPPLY REJECTION (dB)
TA = 25C VS = 12V IS = 10mA PER AMPLIFIER
GAIN (dB)
1 10 FREQUENCY (MHz)
Output Impedance vs Frequency
1000 TA = 25C VS 12V IS PER AMPLIFIER = 2mA 10 IS PER AMPLIFIER = 10mA IS PER AMPLIFIER = 15mA ISHDN (mA)
2.5
SUPPLY CURRENT PER AMPLIFIER (mA)
100
OUTPUT IMPEDANCE ()
1
0.1
0.01 0.01
0.1
1 10 FREQUENCY (MHz)
Differential Harmonic Distortion vs Output Amplitude
f = 1MHz TA = 25C -50 VS = 12V AV = 10 RL = 50 -60 I PER AMPLIFIER = 10mA S HD3 -70 -80 HD2 -90 -100 0 2 4 6 8 10 12 14 16 18 VOUT(P-P)
6301 G16
-40
DISTORTION (dBc)
DISTORTION (dBc)
UW
6301 G10
PSRR vs Frequency
100 90 80 70 60 50 40 30 20 10 0
100
Frequency Response vs Supply Current
30 25 20 15 10 5 0 -5 -10 -15 -20 2mA PER AMPLIFIER 10mA PER AMPLIFIER 15mA PER AMPLIFIER VS = 12V AV = 10
VS = 12V AV = 10 IS = 10mA PER AMPLIFIER
(-) SUPPLY (+) SUPPLY
-10 0.01
0.1
1 10 FREQUENCY (MHz)
100
6301 G11
1k
10k
100k 1M 10M FREQUENCY (Hz)
100M
6301 G12
ISHDN vs VSHDN
35 TA = 25C VS = 12V VSHDNREF = 0V 30 25 20 15 10 5 0
Supply Current vs VSHDN
TA = 25C VS = 12V VSHDNREF = 0V
2.0
1.5
1.0
0.5
100
6301 G13
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VSHDN (V)
6301 G14
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VSHDN (V)
6301 G15
Differential Harmonic Distortion vs Frequency
-40 -45 -50 -55 -60 -65 -70 -75 -80 -85 HD2 HD3 VO = 10VP-P TA = 25C VS = 12V AV = 10 RL = 50 IS PER AMPLIFIER = 10mA
-90 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (kHz)
6301 G17
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LT6301 TYPICAL PERFOR A CE CHARACTERISTICS
Differential Harmonic Distortion vs Supply Current
-40 -45 -50 VO = 10VP-P VS = 12V AV = 10 RL = 50 f = 1MHz, HD3 -60 -65 -70 -75 -80 -85 2 3 4 5 f = 1MHz, HD2 6 7 8 9 10 ISUPPLY PER AMPLIFIER (mA) 11 f = 100kHz, HD2 f = 100kHz, HD3
-55
OUTPUT VOLTAGE (VP-P)
DISTORTION (dBc)
TEST CIRCUIT
SUPPLY BYPASSING TO PINS: 18, 19, 24 AND 25 0.1F 12V RBIAS 4 (SHDN) 3 OR 9 RBIAS TO PINS: 1, 14, 15, 16, 21, 22, 27 AND 28
OUT (+) EIN 49.9 MINICIRCUITS ZSC5-2-2 SPLITTER OUT (-)
6
UW
10k 10k
Undistorted Output Swing vs Frequency
20
15
10 SFDR > 40dB TA = 25C VS = 12V AV = 10 RL = 50 IS PER AMPLIFIER = 10mA 300k 1M 3M FREQUENCY (Hz) 10M
6301 G19
5
0 100k
6301 G18
+
4.7F
12V
+
4.7F 0.1F -12V
+
0.1F 4.7F
+ -
10 A OR C 26 OR 20 VOUT(P-P)
2 OR 8
12.7 -12V 110 0.01F 1k 23 OR 17 5 (SHDNREF) 11 *COILCRAFT X8390-A OR EQUIVALENT VOUTP-P AMPLITUDE SET AT EACH AMPLIFIER OUTPUT DISTORTION MEASURED ACROSS LINE LOAD FOR MATCHING, USE AMPLIFIERS A AND B, OR AMPLIFIERS C AND D 1k RL 50 100 LINE LOAD 110 1:2*
7 OR 13
-
B OR D
12.7
6301 TC
6 OR 12
+
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LT6301
APPLICATIO S I FOR ATIO
The LT6301 is a high speed, 200MHz gain bandwidth product, quad voltage feedback amplifier with high output current drive capability, 500mA source and sink. The LT6301 is ideal for use as a line driver in xDSL data communication applications. The output voltage swing has been optimized to provide sufficient headroom when operating from 12V power supplies in full-rate ADSL applications. The LT6301 also allows for an adjustment of the operating current to minimize power consumption. In addition, the LT6301 is available in a small footprint surface mount package to minimize PCB area. To minimize signal distortion, the LT6301 amplifiers are decompensated to provide very high open-loop gain at high frequency. As a result each amplifier is frequency stable with a closed-loop gain of 10 or more. If a closedloop gain of less than 10 is desired, external frequency compensating components can be used.
SHDN
5I I
2k 2I
2I
1k TO START-UP CIRCUITRY SHDNREF IBIAS TO AMPLIFIERS BIAS CIRCUITRY
6301 F01
IBIAS = 2 ISHDN = ISHDNREF 5 ISUPPLY PER AMPLIFIER (mA) = 64 * IBIAS
Figure 1. Internal Current Biasing Circuitry
30 25 20 15 VS = 12V
V + = 12V
ISUPPLY PER AMPLIFIER (mA)
10
SHDNREF
5 0 7 10 40 70 100 RBIAS (k) 130 160 190
6301 F02
Figure 2. RBIAS to V+ Current Control
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Setting the Quiescent Operating Current Power consumption and dissipation are critical concerns in multiport xDSL applications. Two pins, Shutdown (SHDN) and Shutdown Reference (SHDNREF), are provided to control quiescent power consumption and allow for the complete shutdown of the drivers. The quiescent current should be set high enough to prevent distortion induced errors in a particular application, but not so high that power is wasted in the driver unnecessarily. A good starting point to evaluate the LT6301 is to set the quiescent current to 10mA per amplifier. Pins 4 and 5 set the current for amplifiers A and B and Pins 10 and 11 set the current for amplifers C and D. Each amplifier pair should be controlled separately. The internal biasing circuitry is shown in Figure 1. Grounding the SHDNREF pin and directly driving the SHDN pin with a voltage can control the operating current as seen in the Typical Performance Characteristics. When the SHDN pin is less than SHDNREF + 0.4V, the driver is shut down and consumes typically only 100A of supply current and the outputs are in a high impedance state. Part to part variations, however, will cause inconsistent control of the quiescent current if direct voltage drive of the SHDN pin is used. Using an external resistor, RBIAS, connected in one of two ways provides a much more predictable control of the quiescent supply current. Figure 2 illustrates the effect on supply current per amplifier with RBIAS connected between the SHDN pin and the 12V V + supply of the LT6301 and the approximate design equations. Figure 3 illustrates the same control with RBIAS connected between the SHDNREF pin and ground while the SHDN pin is tied to V +. Either approach is equally effective.
RBIAS SHDN IS PER AMPLIFIER (mA) V + - 1.2V * 25.6 RBIAS + 2k RBIAS = V + - 1.2V * 25.6 - 2k IS PER AMPLIFIER (mA)
W
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7
LT6301
APPLICATIO S I FOR ATIO
45 40
ISUPPLY PER AMPLIFIER (mA)
VS = 12V
35 30 25 20 15 10 5 0 4 7 10 30 50 70
Figure 3. RBIAS to Ground Current Control
Two Control Inputs
RESISTOR VALUES (k) RSHDN TO VCC (12V) RSHDN TO VLOGIC VLOGIC 3V 3.3V 5V 3V 3.3V 5V RSHDN 40.2 43.2 60.4 4.99 6.81 19.6 RC1 11.5 13.0 21.5 8.66 10.7 20.5 RCO 19.1 22.1 36.5 14.3 17.8 34.0 VC0 SUPPLY CURRENT PER AMPLIFIER (mA) H 10 10 10 10 10 10 L 7 7 7 7 7 7 H 5 5 5 5 5 5 L 2 2 2 2 2 2 VLOGIC VC1 0V VC0 RC1 RC0 12V OR VLOGIC RSHDN SHDN 2k
VC1 H H L L
One Control Input
RESISTOR VALUES (k) RSHDN TO VCC (12V) RSHDN TO VLOGIC VLOGIC 3V 3.3V 5V 3V 3.3V 5V RSHDN 40.2 43.2 60.4 4.99 6.81 19.6 RC 7.32 8.25 13.7 5.49 6.65 12.7 VC H L SUPPLY CURRENT PER AMPLIFIER (mA) 10 10 10 10 10 10 2 2 2 2 2 2
6301 F04
Figure 4. Providing Logic Input Control of Operating Current
Logic Controlled Operating Current The DSP controller in a typical xDSL application can have I/O pins assigned to provide logic control of the LT6301 line driver operating current. As shown in Figure 4 one or two logic control inputs can control two or four different operating modes. The logic inputs add or subtract current to the SHDN input to set the operating current. The one logic input example selects the supply current to be either full power, 10mA per amplifier or just 2mA per amplifier, which significantly reduces the driver power consumption
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V + = 12V SHDN V + - 1.2V * 64 IS PER AMPLIFIER (mA) RBIAS + 5k V + - 1.2V * 64 - 5k IS PER AMPLIFIER (mA) RBIAS = SHDNREF RBIAS
W
UU
90 100 130 150 170 190 210 230 250 270 290 RBIAS (k)
6301 F03
SHDNREF
12V OR VLOGIC VLOGIC 0V VC RSHDN SHDN 2k
RC
SHDNREF
while maintaining less than 2 output impedance to frequencies less than 1MHz. This low power mode retains termination impedance at the amplifier outputs and the line driving back termination resistors. With this termination, while a DSL port is not transmitting data, it can still sense a received signal from the line across the backtermination resistors and respond accordingly. The two logic input control provides two intermediate (approximately 7mA per amplifier and 5mA per amplifier) operating levels between full power and termination modes.
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LT6301
APPLICATIO S I FOR ATIO
These modes can be useful for overall system power management when full power transmissions are not necessary. Contact LTC Applications for single supply design information. Shutdown and Recovery The ultimate power saving action on a completely idle port is to fully shut down the line driver by pulling the SHDN pin to within 0.4V of the SHDNREF potential. As shown in Figure 5 complete shutdown occurs in less than 10s and, more importantly, complete recovery from the shut down state to full operation occurs in less than 2s. The biasing circuitry in the LT6301 reacts very quickly to bring the amplifiers back to normal operation.
VSHDN SHDNREF = 0V
AMPLIFIER OUTPUT
6301 F05
Figure 5. Shutdown and Recovery Timing
12V
20mA DC
24.9k - SETS IQ PER AMPLIFIER = 10mA
+IN
+
A
2VRMS SHDN 17.4
-
1k 110 1000pF ILOAD = 57mARMS 110 1k 1:1.7
* *
-
B -IN
+
-12V
SHDNREF
-2VRMS
Figure 6. Estimating Line Driver Power Dissipation
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Power Dissipation and Heat Management xDSL applications require the line driver to dissipate a significant amount of power and heat compared to other components in the system. The large peak to RMS variations of DMT and CAP ADSL signals require high supply voltages to prevent clipping, and the use of a step-up transformer to couple the signal to the telephone line can require high peak current levels. These requirements result in the driver package having to dissipate significant amounts of power. Several multiport cards inserted into a rack in an enclosed central office box can add up to many, many watts of power dissipation in an elevated ambient temperature environment. The LT6301 has builtin thermal shutdown circuitry that will protect the amplifiers if operated at excessive temperatures, however data transmissions will be seriously impaired. It is important in the design of the PCB and card enclosure to take measures to spread the heat developed in the driver away to the ambient environment to prevent thermal shutdown (which occurs when the junction temperature of the LT6301 exceeds 165C). Estimating Line Driver Power Dissipation Figure 6 is a typical ADSL application shown for the purpose of estimating the power dissipation in the line driver. Due to the complex nature of the DMT signal,
100 3.16VRMS 17.4
6301 F06
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9
LT6301
APPLICATIO S I FOR ATIO
which looks very much like noise, it is easiest to use the RMS values of voltages and currents for estimating the driver power dissipation. The voltage and current levels shown for this example are for a full-rate ADSL signal driving 20dBm or 100mWRMS of power on to the 100 telephone line and assuming a 0.5dBm insertion loss in the transformer. The quiescent current for the LT6301 is set to 10mA per amplifier. The power dissipated in the LT6301 is a combination of the quiescent power and the output stage power when driving a signal. The two pairs of amplifiers are configured to place a differential signal on two lines. The Class AB output stage in each amplifier will simultaneously dissipate power in the upper power transistor of one amplifier, while sourcing current, and the lower power transistor of the other amplifier, while sinking current. The total device power dissipation is then: PD = PQUIESCENT + PQ(UPPER) + PQ(LOWER) PD = (V+ - V-) * IQ + (V+ - VOUTARMS) * ILOAD + (V - - VOUTBRMS) * ILOAD With no signal being placed on the line and the amplifier biased for 10mA per amplifier supply current, the quiescent driver power dissipation is: PDQ = [24V * 10mA] * 4 = 960mW This can be reduced in many applications by operating with a lower quiescent current value or shutting down the part during idle conditions. When driving a load, a large percentage of the amplifier quiescent current is diverted to the output stage and
25
20
TOTAL IQ (mA)
15
10
5
0 -240
-200
-160
-120
-80 -40 0 40 80 120 ILOAD (mA) (ONE DIFFERENTIAL DRIVER)
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becomes part of the load current. Figure 7 illustrates the total amount of biasing current flowing between the + and - power supplies through the amplifiers as a function of load current for one differential driver. As much as 60% of the quiescent no load operating current is diverted to the load. At full power to both lines the total package power dissipation is: PD(FULL) = [24V * 8mA + (12V - 2VRMS) * 57mARMS + [|-12V - (- 2VRMS)|] * 57mARMS] * 2 PD(FULL) = [192mW + 570mW + 570mW] * 2 = 2.664W* The junction temperature of the driver must be kept less than the thermal shutdown temperature when processing a signal. The junction temperature is determined from the following expression: TJ = TAMBIENT (C) + PD(FULL) (W) * JA (C/W) JA is the thermal resistance from the junction of the LT6301 to the ambient air, which can be minimized by heat-spreading PCB metal and airflow through the enclosure as required. For the example given, assuming a maximum ambient temperature of 50C and keeping the junction temperature of the LT6301 to 150C maximum, the maximum thermal resistance from junction to ambient required is: JA(MAX) = 150C - 50C = 37.5C / W 2.664W
*Design techniques exist to significantly reduce this value (See Line Driving Back Termination).
160 200 240
6301 F07
W
UU
Figure 7. IQ vs ILOAD
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LT6301
APPLICATIO S I FOR ATIO
Heat Sinking Using PCB Metal
Designing a thermal management system is often a trial and error process as it is never certain how effective it is until it is manufactured and evaluated. As a general rule, the more copper area of a PCB used for spreading heat away from the driver package, the more the operating junction temperature of the driver will be reduced. The limit to this approach however is the need for very compact circuit layout to allow more ports to be implemented on any given size PCB. To best extract heat from the FE28 package, a generous area of top layer PCB metal should be connected to the four corner pins (Pins 1, 14, 15 and 28). These pins are fused to the leadframe where the LT6301 die are attached. The package also has an exposed metal heat sinking pad on the bottom side which, when soldered to the PCB top layer metal, directly conducts heat away from the IC junction. Soldering the thermal pad to the board produces a thermal resistance from junction to case, JC, of approximately 3C/W. Important Note: The metal planes used for heat sinking the LT6301 are electrically connected to the negative supply potential of the driver, typically -12V. These planes must be isolated from any other power planes used in the board design. Fortunately xDSL circuit boards use multiple layers of metal for interconnection of components. Areas of metal beneath the LT6301 connected together through several small 13 mil vias can be effective in conducting heat away from the driver package. The use of inner layer metal can free up top and bottom layer PCB area for external component placement. When PCB cards containing multiple ports are inserted into a rack in an enclosed cabinet, it is often necessary to provide airflow through the cabinet and over the cards. This is also very effective in reducing the junction-toambient thermal resistance of each line driver. To a limit, this thermal resistance can be reduced approximately 5C/W for every 100lfpm of laminar airflow.
VI RC CC (OPTIONAL)
Figure 8. Compensation for Inverting Gains
+
-
U
Layout and Passive Components With a gain bandwidth product of 200MHz the LT6301 requires attention to detail in order to extract maximum performance. Use a ground plane, short lead lengths and a combination of RF-quality supply bypass capacitors (i.e., 0.1F). As the primary applications have high drive current, use low ESR supply bypass capacitors (1F to 10F). The four V + pins (Pins 18, 19, 24, 25) separately provide power to each amplifier and should be shorted together with leads as short as possible to the bypass capacitors. The parallel combination of the feedback resistor and gain setting resistor on the inverting input can combine with the input capacitance to form a pole that can cause frequency peaking. In general, use feedback resistors of 1k or less. Compensation The LT6301 is stable in a gain 10 or higher for any supply and resistive load. It is easily compensated for lower gains with a single resistor or a resistor plus a capacitor. Figure 8 shows that for inverting gains, a resistor from the inverting node to AC ground guarantees stability if the parallel combination of RC and RG is less than or equal to RF/9. For lowest distortion and DC output offset, a series capacitor, CC, can be used to reduce the noise gain at lower frequencies. The break frequency produced by RC and CC should be less than 5MHz to minimize peaking. Figure 9 shows compensation in the noninverting configuration. The RC, CC network acts similarly to the inverting case. The input impedance is not reduced because the network is bootstrapped. This network can also be placed between the inverting input and an AC ground.
RF RG VO -RF = RG VI VO (RC || RG) RF/9 1 < 5MHz 2RCCC
6301 F08
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sn6301 6301f
11
LT6301
APPLICATIO S I FOR ATIO
VI RC CC (OPTIONAL)
RF VO =1+ VI RG VO (RC || RG) RF/9 1 < 5MHz 2RCCC
RF RG
Figure 9. Compensation for Noninverting Gains
Another compensation scheme for noninverting circuits is shown in Figure 10. The circuit is unity gain at low frequency and a gain of 1 + RF/RG at high frequency. The DC output offset is reduced by a factor of ten. The techniques of Figures 9 and 10 can be combined as shown in Figure 11. The gain is unity at low frequencies, 1 + RF/RG at mid-band and for stability, a gain of 10 or greater at high frequencies.
VO = 1 (LOW FREQUENCIES) VI R = 1 + F (HIGH FREQUENCIES) RG RG RF/9 1 < 5MHz 2RGCC
Vi
VO
RF RG CC
Figure 10. Alternate Noninverting Compensation
VI RC CC
VO
VI
RF RG CBIG
R = 1 + F AT MEDIUM FREQUENCIES RG =1+ RF AT HIGH FREQUENCIES (RC || RG)
6301 F11
RG
Figure 11. Combination Compensation
Figure 12. Standard Cable/Line Back Termination
12
-
VO = 1 AT LOW FREQUENCIES VI
+
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6301 F09
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- +
In differential driver applications, as shown on the first page of this data sheet, it is recommended that the gain setting resistor be comprised of two equal value resistors connected to a good AC ground at high frequencies. This ensures that the feedback factor of each amplifier remains less than 0.1 at any frequency. The midpoint of the resistors can be directly connected to ground, with the resulting DC gain to the VOS of the amplifiers, or just bypassed to ground with a 1000pF or larger capacitor. Line Driving Back-Termination The standard method of cable or line back-termination is shown in Figure 12. The cable/line is terminated in its characteristic impedance (50, 75, 100, 135, etc.). A back-termination resistor also equal to the chararacteristic impedance should be used for maximum pulse fidelity of outgoing signals, and to terminate the line for incoming signals in a full-duplex application. There are three main drawbacks to this approach. First, the power dissipated in the load and back-termination resistors is equal so half of the power delivered by the amplifier is wasted in the termination resistor. Second, the signal is halved so the gain of the amplifer must be doubled to have the same overall gain to the load. The increase in gain increases noise and decreases bandwidth (which can also increase distortion). Third, the output swing of the amplifier is doubled which can limit the power it can deliver to the load for a given power supply voltage. An alternate method of back-termination is shown in Figure 13. Positive feedback increases the effective backtermination resistance so RBT can be reduced by a factor
CABLE OR LINE WITH CHARACTERISTIC IMPEDANCE RL RBT VO RL RF RBT = RL VO 1 = (1 + RF/RG) VI 2
6301 F12
-
+
-
+
6301 F10
sn6301 6301f
LT6301
APPLICATIO S I FOR ATIO
RP2 VI
VP
RG
RP2/(RP2 + RP1) VO = VI
()
1+ RF RG
1 + 1/n
RP1 - RP2 + RP1
-VI
Figure 13. Back Termination Using Postive Feedback
Figure 14. Back Termination Using Differential Postive Feedback
of n. To analyze this circuit, first ground the input. As RBT = RL/n, and assuming RP2>>RL we require that: VA = VO (1 - 1/n) to increase the effective value of RBT by n. VP = VO (1 - 1/n)/(1 + RF/RG) VO = VP (1 + RP2/RP1) Eliminating VP, we get the following: (1 + RP2/RP1) = (1 + RF/RG)/(1 - 1/n) For example, reducing RBT by a factor of n = 4, and with an amplifer gain of (1 + RF/RG) = 10 requires that RP2/RP1 = 12.3. Note that the overall gain is increased:
and assuming RP >> RL, we require VA = VO (1 - 1/n) solving RF/RP = 1 - 1/n So to reduce the back-termination by a factor of 3 choose RF/RP = 2/3. Note that the overall gain is increased to: VO/VI = (1 + RF/RG + RF/RP)/[2(1 - RF/RP)] Using positive feedback is often referred to as active termination. Figure 16 shows a full-rate ADSL line driver incorporating positive feedback to reduce the power lost in the back termination resistors by 40% yet still maintains the proper impedance match to the100 characteristic line impedance. This circuit also reduces the transformer turns ratio over the standard line driving approach resulting in lower peak current requirements. With lower current and less power loss in the back termination resistors, this driver dissipates only 1W of power, a 30% reduction. While the power savings of positive feedback are attractive there is one important system consideration to be addressed, received signal sensitivity. The signal received
RP2 / (RP2 + RP1) VO = VI (1+ 1/n) / (1+ RF /RG ) - RP1/(RP2 + RP1)
[
][
]
A simpler method of using positive feedback to reduce the back-termination is shown in Figure 14. In this case, the drivers are driven differentially and provide complementary outputs. Grounding the inputs, we see there is inverting gain of -RF/RP from -VO to VA VA = VO (RF/RP)
+
-
-
+
RP1
VA RBT RL RF RL FOR RBT = n
VO
6301 F13
( )(
1 RP1 R =1- 1+ F n RG RP1 + RP2
)
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VI
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+ -
RF RG RP RP RG RF
VA RBT VO FOR RBT = n= RL 1 RF RP RL n
1-
RL
VO = VI
RR 1+ F + F RG RP 2 1-
()
RF RP
RBT -VA -VO
6301 F14
sn6301 6301f
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LT6301
APPLICATIO S I FOR ATIO
from the line is sensed across the back termination resistors. With positive feedback, signals are present on both ends of the RBT resistors, reducing the sensed amplitude. Extra gain may be required in the receive channel to compensate, or a completely separate receive path may be implemented through a separate line coupling transformer. Considerations for Fault Protection The basic line driver design, shown on the front page of this data sheet, presents a direct DC path between the outputs of the two amplifiers. An imbalance in the DC biasing potentials at the noninverting inputs through either a fault condition or during turn-on of the system can create a DC voltage differential between the two amplifier outputs. This condition can force a considerable amount of current to flow as it is limited only by the small valued back-termination resistors and the DC resistance of the transformer primary. This high current can possibly cause the power supply voltage source to drop significantly impacting overall system performance. If left unchecked, the high DC current can heat the LT6301 to thermal shutdown.
+IN
+
1/4 LT6301
-
1k 110 1000pF 1:2
* *
LINE LOAD 1k
110
-
1/4 LT6301 -IN
+
-12V
Figure 15. Protecting the Driver Against Load Faults and Line Transients
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Using DC blocking capacitors, as shown in Figure 15, to AC couple the signal to the transformer eliminates the possibility for DC current to flow under any conditions. These capacitors should be sized large enough to not impair the frequency response characteristics required for the data transmission. Another important fault related concern has to do with very fast high voltage transients appearing on the telephone line (lightning strikes for example). TransZorbs(R), varistors and other transient protection devices are often used to absorb the transient energy, but in doing so also create fast voltage transitions themselves that can be coupled through the transformer to the outputs of the line driver. Several hundred volt transient signals can appear at the primary windings of the transformer with current into the driver outputs limited only by the back termination resistors. While the LT6301 has clamps to the supply rails at the output pins, they may not be large enough to handle the significant transient energy. External clamping diodes, such as BAV99s, at each end of the transformer primary help to shunt this destructive transient energy away from the amplifier outputs.
TransZorb is a registered trademark of General Instruments, GSI
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12V 12V -12V 24.9k 0.1F SHDN 12.7 BAV99
0.1F 12.7 SHDNREF 12V -12V
6301 F15
BAV99
sn6301 6301f
LT6301
SI PLIFIED SCHE ATIC
V+
-IN
V-
PACKAGE DESCRIPTIO
7.56 (.298)
6.60 0.10 4.50 0.10 SEE NOTE 4
RECOMMENDED SOLDER PAD LAYOUT
4.30 - 4.50* (.169 - .177) 0 - 8
0.09 - 0.20 (.0036 - .0079)
0.45 - 0.75 (.018 - .030)
NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
W
W
(one amplifier shown)
Q9 Q10 Q13 Q17 Q3 Q1 R1 Q2 Q4 Q8 Q16 Q12 Q11
6301 SS
Q7 Q6 Q5
C1 +IN C2
Q14 OUT Q15 Q18
FE Package 28-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation EA
9.60 - 9.80* (.378 - .386) 7.56 (.298) 28 2726 25 24 23 22 21 20 19 18 1716 15
3.05 (.120) 0.45 0.05
EXPOSED PAD HEAT SINK ON BOTTOM OF PACKAGE
3.05 6.40 (.120) BSC
1.05 0.10 0.65 BSC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1.20 (.047) MAX
0.65 (.0256) BSC
0.195 - 0.30 (.0077 - .0118)
0.05 - 0.15 (.002 - .006)
FE28 (EA) TSSOP 0203
4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE
sn6301 6301f
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LT6301
TYPICAL APPLICATIO
+IN
* *
182 1000pF
182
-IN
RELATED PARTS
PART NUMBER LT1361 LT1739 LT1794 LT1795 LT1813 LT1886 LT1969 LT6300 DESCRIPTION Dual 50MHz, 800V/s Op Amp Dual 500mA, 200MHz xDSL Line Driver Dual 500mA, 200MHz xDSL Line Driver Dual 500mA, 50MHz Current Feedback Amplifier Dual 100MHz, 750V/s, 8nV/Hz Op Amp Dual 200mA, 700MHz Op Amp Dual 200mA, 700MHz Op Amp with Power Control Dual 500mA, 200MHz, xDSL Line Driver COMMENTS 15V Operation, 1mV VOS, 1A IB Low Cost ADSL CO Driver, Low Power ADSL CO Driver, Extended Output Swing, Low Power Shutdown/Current Set Function, ADSL CO Driver Low Noise, Low Power Differential Receiver, 4mA/Amplifier 12V Operation, 7mA/Amplifier, ADSL CPE Modem Line Driver 12V Operation, MSOP Package, ADSL CPE Modem Line Driver ADSL CO Driver in SSOP Package
16
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507
q
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12V 24.9k
+
1/4 LT6301
SHDN
13.7
-
1k 1.65k 1.65k 1k *COILCRAFT X8502-A OR EQUIVALENT 1W DRIVER POWER DISSIPATION 1.15W POWER CONSUMPTION
6301 F16
1:1.2* 100 LINE
-
1/4 LT6301
13.7 SHDNREF
+
-12V
Figure 16. ADSL Line Driver Using Active Termination
sn6301 6301f LT/TP 0303 2K * PRINTED IN THE USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2001

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